Created 06/18/03; edits 02/17/08, 07/23/15

# on Addition and Subtraction Instructions

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1. How many bits are the operands of the ALU?

 A.    Always 32. B.    8, 16, or 32 C.    32 or 64 D.    Any number of bits up to 32.

2. What procedure does the `addu` instruction call for?

 A.    The binary addition algorithm. B.    The unsigned addition algorithm. C.    The bit-wise addition algorithm. D.    The universal addition algorithm.

3. What type of data may be in the registers used as operands for the `addu` instruction?

 A.    32-bit unsigned in both registers. B.    32-bit two's complement in both registers. C.    32-bit unsigned or 32-bit two's complement, the same type in each register. D.    32-bit unsigned or 32-bit two's complement, either type in either register.

4. What is a trap?

 A.    A trap is an interruption in the normal machine cycle. B.    A trap is an instruction that captures data. C.    A trap is a shortened version of a normal 32-bit instruction. D.    A trap is a bus signal that says that something is wrong.

5. Write the instruction that adds the contents of registers \$8 and \$9 and puts the result in register \$13.

 A.    ``` add \$8,\$9,\$13 ``` B.    ``` addi \$8,\$9,\$13 ``` C.    ``` addu \$13,\$8,\$9 ``` D.    ``` add \$9,\$8,\$13 ```

6. Can the immediate operand of an `addiu` instruction be a two's complement negative integer?

 A.    No. The immediate operand is zero-extended to 32 bits. B.    Yes. When the instruction is executed, the immediate operand is sign-extended to 32 bits. C.    No. A 16-bit immediate operand is too small for two's complement. D.    Yes. Immediate operands are always two's complement.

7. What is it called when bit 15 of a 16-bit immediate operand is copied to the 16 bits to its left to form a 32-bit operand?

 A.    Sign extention B.    Bit extention C.    Zero extention D.    Immediate extention

8. Write an instruction that adds the value 12 to the value in register \$6. Use an instruction which ignores overflow.

 A.    ``` add \$6,12 ``` B.    ``` addi \$6,\$0,12 ``` C.    ``` addiu \$6,\$6,12 ``` D.    ``` addi \$6,12 ```

9. What integer subtraction instruction uses two operand registers, one result register, and does not trap if overflow is detected?

 A.    ``` subu ``` B.    ``` sub ``` C.    ``` subi ``` D.    ``` subiu ```

10. Which instruction loads register \$17 with a -99?

 A.    ``` addiu \$17,\$0,-99 ``` B.    ``` sub \$17,\$0,-99 ``` C.    ``` addiu \$17,-99 ``` D.    ``` subu \$17,\$17,99 ```

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