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Answer:

mul $v2,$s3,$t0

Translates into:

mult  $s3, $t0

mflo  $v2

mul Pseudoinstruction

The mul pseudoinstruction makes it look as if MIPS has a 32-bit multiply instruction that places its 32-bit result:

mul  d,s,t # multiply $s by $t. put the
           # result in $d
           # (pseudoinstruction)

There is no overflow checking. The bits of hi are not examined nor saved. There are several other pseudoinstructions that examine hi and perform various actions on overflow. We won't use them.

There is a similar instruction for division. The basic instructions  div s,t  and  divu s,t  put their results in MIPS registers hi and lo. The 32-bit quotient goes in lo and the 32-bit remainder goes in hi. To move the quotient into a register, mflo is used.


QUESTION 7:

Finish the translation. The operand registers are $s1 and $s2, the destination register is $t0.

div $t0,$s1,$s2

Translates into:

div   , 

mflo